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cy7c024/024a/0241 cy7c025/0251 4k x 16/18 and 8k x 16/18 dual-port static ram with sem, int, busy cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-06035 rev. *f revised october 13, 2010 features true dual-ported memory cells, which allow simultaneous reads of the same memory location 4k x 16 organization (cy7c024/024a [1] ) 4k x 18 organization (cy7c0241) 8k x 16 organization (cy7c025) 8k x 18 organization (cy7c0251) 0.65 micron cmos for optimum speed and power high speed access: 15 ns low operating power: i cc = 150 ma (typ) fully asynchronous operation automatic power down expandable data bus to 32/36 bits or more using master/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication separate upper-byte and lower-byte control pin select for master or slave available in 84-pin (pb-free) plcc, 84-pin plcc, 100-pin (pb-free) tqfp, and 100-pin tqfp functional description the cy7c024/024a/0241 and cy7c025/0251 are low power cmos 4k x 16/18 and 8k x 16/18 dual-port static rams. various arbitration schemes are included on the cy7c024/ 0241 and cy7c025/0251 to handle situatio ns when multiple processors access the same piece of data. two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. the cy7c024/ 0241 and cy7c025/0251 can be used as standalone 16 or 18-bit dual-port static rams or multiple devices can be combined to function as a 32-/36-bit or wider master/ slav e dual-port static ram. an m/s pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interprocessor/multiprocessor des igns, communications status buffering, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy signals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) permits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semap hore) at any time. control of a semaphore indicates that a shared resource is in use. an automatic power down feature is controlled independently on each port by a chip select (ce ) pin. the cy7c024/024a/0241 and cy 7c025/0251 are available in 84-pin pb-free plccs, 84-pin plccs (cy7c024 and cy7c025 only), 100-pin pb-free thin quad plastic flatplack (tqfp), and 100-pin thin quad plastic flatpack. note 1. cy7c024 and cy7c024a are functionally identical. [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 2 of 19 logic block diagram l l l oe l a 0l r/w r ub r ce r oe r ce l oe l ub l ub r i/o 8l ?i/o 15l interrupt semaphore arbitration control i/o memory array address decoder sem l sem r busy l int l int r m/s control i/o lb l lb r i/o 0l ? i/o 7l r/w l r/w r lb r ce r oe r a 0r i/o 8r i/o 15r busy r i/o 0r i/o 7r (cy7c025/0251) a 12l a 12r (cy7c025/0251) [2] [2] ? ? address decoder a 11l a 11r [3] [4] [3] [4] pin configurations figure 1. 84-pin plcc (top view) notes 2. busy is an output in master mode and an input in slave mode. 3. i/o 0 ?i/o 8 on the cy7c0241/0251. 4. i/o 9 ?i/o 17 on the cy7c0241/0251. 5. a 12l on the cy7c025/0251. 6. a 12r on the cy7c025/0251. l l l a 7l oe ce nc i/o i/o i/o i/o i/o i/o a 6l a 5l a 4l a 3l a 2l int l busy l m/s busy r a 1r a 2r i/o 8l i/o 9l i/o 10l i/o 11l i/o 12l i/o 13l i/o 15l v cc i/o 0r i/o 2r i/o 1r i/o 3r i/o 4r i/o 5r a a a a a 3r a 4r a 5r a 6r i/o 6r i/o 7r i/o 8r gnd i/o 14l a 1l i/o r/w sem ub a 0l gnd int r a 0r gnd gnd 7l 6l 5l 4l 3l 2l 0l l l 11l 10l 9l 8l i/o 1l v cc lb l oe ce i/o i/o i/o i/o i/o a a a a gnd i/o r/w sem ub 9r 10r 11r 12r 13r 15r r r r r 10r 9r 8r 7r i/o 14r r lb r a 11r nc gnd v cc 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 cy7c024/024a/025 [5] [6] [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 3 of 19 figure 2. 100-pin tqfp (top view) pin configurations (continued) 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc nc nc i/o 10l i/o 11l i/o 15l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 14l gnd i/o 12l i/o 13l a 1r a 2r a 3r a 4r nc nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 8l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 8r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r ? r r/w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c024/5 r/w l [5] [6] pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ?a 11/12l a 0r ?a 11/12r address i/o 0l ?i/o 15/17l i/o 0r ?i/o 15/17r data bus input/output sem l sem r semaphore enable ub l ub r upper byte select lb l lb r lower byte select int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 4 of 19 architecture the cy7c024/024a/0241 and cy7c025/0251 consist of an array of 4k words of 16/18 bits each and 8k words of 16/18 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be used for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the cy7c024/024a/0241 and cy7c025/0251 can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the cy7c024/024a/0241 and cy7c025/0251 have an automatic power down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w to guarantee a valid write. a write operation is controlled by either the r/w pin (see figure 7 ) or the ce pin (see figure 8 ). required inputs for non contention operations are summarized in ta b l e 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is r ead on the output; otherwise the data read is not deterministic. data is valid on the port t ddd after the data is presen ted on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data is available t ace after ce or t doe after oe is asserted. if the user of the cy7c024/024a/0241 or cy7c025/0251 wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (fff for the cy7c024/024a/0241, 1fff for the cy7c025/0251) is the mailbox for the right port and the second-highest memory location (ffe for the cy7c024/024a/0241, 1ffe for the cy7c025/0251) is the mailbox for the left port. when one port writes to the other port?s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other port?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and thus resetting the interrupt to it. if your application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2 on page 5 . busy the cy7c024/024a/0241 and cy7c025/0251 provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports? ce s are asserted and an address match occurs within t ps of each other, the busy logic determines which port has access. if t ps is violated, one port definitely gains permission to the location, but which one is not predictable. busy is asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this allows the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ). otherwise, the slave chip may begin a write cycle durin g a contention si tuation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c024/024a/0241 and cy7c025/0251 provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resour ce is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for tsop before attempting to read the semaphore. the semaphore value is available t swrd + t doe after the rising edge of the semaphore write. if the left port was succe ssful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. selection guide parameter 7c024/024a/0241?15 7c025/0251?15 7c024/0241?25 7c025/0251?25 7c024/0241?35 7c025/0251?35 7c024/0241?55 7c025/0251?55 maximum access time (ns) 15 25 35 55 typical operating current (ma) 190 170 160 150 typical standby current for i sb1 (ma) 50 40 30 20 [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 5 of 19 semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a0?2 represents the semaphore address. oe and r/w are used in the same manner as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an av ailable semaphore, a one appears at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if t he left port now relinquishes control by writing a one to the semapho re, the semaphore is set to one for both sides. however, if the right port had requested the semaphore (written a zero) while the left port had control, the right port immediately owns the semaphore as soon as the left port released it. ta b l e 3 shows sample semaphore operations. when reading a semaphore, all sixteen/eighteen data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to access the semaphore within t sps of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore table 1. non-contending read/write inputs outputs operation ce r/w oe ub lb sem i/o 0 ? i/o 7 [3] i/o 8 ? i/o 15 [4] h x x x x h high z high z deselected: power down x x x h h h high z high z deselected: power down l l x l h h high z data in write to upper byte only l l x h l h data in high z write to lower byte only l l x l l h data in data in write to both bytes l h l l h h high z data out read upper byte only l h l h l h data out high z read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) [7] function left port right port r/w l ce l oe l a 0 l ?11 l int l r/w r ce r oe r a 0r?11r int r set right int r flag l l x (1)fff x x x x x l [9] reset right int r flag x x x x x x l l (1)fff h [8] set left int l flag x x x x l [8] llx(1)ffex reset left int l flag x l l (1)ffe h [9] xxx x x [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 6 of 19 table 3. semaphore operation example function i/o 0 ? i/o 15/17 left i/o 0 ? i/o 15/17 right status no action 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore. left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore-free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore-free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore-free notes 7. a 0l?12l and a 0r?12r , 1fff/1ffe for the cy7c025. 8. if busy r =l, then no change. 9. if busy l =l, then no change. [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 7 of 19 maximum ratings [10] exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature ................ .............. ... ?65c to +150c ambient temperature with power applied ............ ............... .............. ... ?55c to +125c supply voltage to ground potentia l................?0.3v to +7.0v dc voltage applied to outputs in high-z state................................................?0.5v to +7.0v dc input voltage [11] ........................................?0.5v to +7.0v output current into outputs (low)............................. 20 ma static discharge voltage....... ........... ............ ............ > 2001v (per mil-std-883, method 3015) latch up current ................................................... > 200 ma operating range range ambient temperature v cc commercial 0c to +70c 5v ? 10% industrial ?40c to +85c 5v ? 10% electrical characteristics over the operating range parameter description test conditions 7c024/024a/0241?15 7c025/0251?15 7c024/024a/0241?25 7c025/0251?25 unit min typ max min typ max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min, i ol = 4.0 ma 0.4 0.4 v v ih input high voltage 2.2 2.2 v v il input low voltage ?0.7 0.8 ?0.7 0.8 v i ix input leakage current gnd ? v i ? v cc ?10 +10 ?10 +10 ? a i oz output leakage current output disabled, gnd ? v o ? v cc ?10 +10 ?10 +10 ? a i cc operating current v cc = max, i out = 0 ma, outputs disabled com?l 190 300 170 250 ma ind 200 320 170 290 i sb1 standby current (both ports ttl levels) ce l and ce r ? v ih , f = f max [12] com?l 50 70 40 60 ma ind 50 70 75 i sb2 standby current (one port ttl level) ce l or ce r ? v ih , f = f max [12] com?l 120 180 100 150 ma ind 120 180 100 170 i sb3 standby current (both ports cmos levels) both ports ce and ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, f = 0 [12] com?l 3 15 3 15 ma ind 3 15 3 15 i sb4 standby current (both ports cmos levels) one port ce l or ce r ? v cc ? 0.2v, v in ?? v cc ? 0.2v or v in ? 0.2v, active port outputs, f = f max [12] com?l 110 160 90 130 ma ind 110 160 90 150 electrical characteristics over the operating range parameter description test conditions 7c024/024a/0241?35 7c025/0251?35 7c024/024a/0241?55 7c025/0251?55 unit min typ max min typ max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min, i ol = 4.0 ma 0.4 0.4 v v ih input high voltage 2.2 2.2 v v il input low voltage ?0.7 0.8 ?0.7 0.8 v i ix input leakage current gnd ? v i ? v cc ?10 +10 ?10 +10 ? a i oz output leakage current output disabled, gnd ? v o ? v cc ?10 +10 ?10 +10 ? a notes 10. the voltage on any input or i/o pin cann ot exceed the power pin during power up 11. pulse width < 20 ns. 12. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 8 of 19 i cc operating current v cc = max, i out = 0 ma, outputs disabled com?l 160 230 150 230 ma ind 160 260 150 260 i sb1 standby current (both ports ttl levels) ce l and ce r ? v ih , f = f max [12] com?l 30 50 20 50 ma ind 30 65 20 65 i sb2 standby current (one port ttl level) ce l or ce r ? v ih , f = f max [12] com?l 85 135 75 135 ma ind 85 150 75 150 i sb3 standby current (both ports cmos levels) both ports ce and ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, f = 0 [12] com?l 3 15 3 15 ma ind 3 15 3 15 i sb4 standby current (both ports cmos levels) one port ce l or ce r ? v cc ? 0.2v, v in ? v cc ? 0.2v or v in ? 0.2v, active port outputs, f = f max [12] com?l 80 120 70 120 ma ind 80 135 70 135 electrical characteristics over the operating range (continued) parameter description test conditions 7c024/024a/0241?35 7c025/0251?35 7c024/024a/0241?55 7c025/0251?55 unit min typ max min typ max capacitance [13] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf figure 3. ac test loads and waveforms note 13. tested initially and after any design or process changes that may affect these parameters. 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 893 ? 5v output r2 = 347 ? c= 30 pf v th =1.4v output c= 30pf (b) thvenin equivalent (load 1) (c) three-state delay (load 3) c = 30 pf output load (load 2) r1 = 893 ? r2 = 347 ? 5v output c= 5pf r th = 250 ? ? ? [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 9 of 19 switching characteristics over the operating range [14] parameter description 7c024/024a/0241?15 7c025/0251?15 7c024/024a/0241?25 7c025/0251?25 7c024/024a/0241?35 7c025/0251?35 7c024/024a/0241?55 7c025/0251?55 unit min max min max min max min max read cycle t rc read cycle time 15 25 35 55 ns t aa address to data valid 15 25 35 55 ns t oha output hold from address change 33 33ns t ace [15] ce low to data valid 15 25 35 55 ns t doe oe low to data valid 10 13 20 25 ns t lzoe [16, 17, 18] oe low to low z 3 3 3 3 ns t hzoe [16, 17, 18] oe high to high z 10 15 20 25 ns t lzce [16, 17, 18] ce low to low z 3 3 3 3 ns t hzce [16, 17, 18] ce high to high z 10 15 20 25 ns t pu [18] ce low to power up 0 0 0 0 ns t pd [18] ce high to power down 15 25 25 55 ns t abe [15] byte enable access time 15 25 35 55 ns write cycle t wc write cycle time 15 25 35 55 ns t sce [15] ce low to write end 12 20 30 35 ns t aw address setup to write end 12 20 30 35 ns t ha address hold from write end 0 0 0 0 ns t sa [15] address setup to write start 0 0 0 0 ns t pwe write pulse width 12 20 25 35 ns t sd data setup to write end 10 15 15 20 ns t hd data hold from write end 0 0 0 0 ns t hzwe [17, 18] r/w low to high z 10 15 20 25 ns t lzwe [17, 18] r/w high to low z 0 0 0 0 ns t wdd [19] write pulse to data delay 30 50 60 70 ns t ddd [19] write data valid to read data valid 25 35 35 45 ns notes 14. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 30 pf load capacitance. 15. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 16. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 17. test conditions used are load 3. 18. this parameter is guaranteed but not tested. 19. for information on port-to-port delay through ram cells from writing port to reading port, refer to figure 11 . [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 10 of 19 data retention mode the cy7c024/024a/0241 is designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules insure data retention: 1. chip enable (ce ) must be held high during data retention, within v cc to v cc ? 0.2v. 2. ce must be kept between v cc ? 0.2v and 70% of v cc during the power up and power down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (4.5v). busy timing [20] t bla busy low from address match 15 20 20 45 ns t bha busy high from address mismatch 15 20 20 40 ns t blc busy low from ce low 15 20 20 40 ns t bhc busy high from ce high 15 20 20 35 ns t ps port setup for priority 5 5 5 5 ns t wb r/w high after busy (slave) 0 0 0 0 ns t wh r/w high after busy high (slave) 13 20 30 40 ns t bdd [21] busy high to data valid note 21 note 21 note 21 note 21 ns interrupt timing [20] t ins int set time 15 20 25 30 ns t inr int reset time 15 20 25 30 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 12 15 20 ns t swrd sem flag write to read time 5 10 10 15 ns t sps sem flag contention window 5 10 10 15 ns t saa sem address access time 15 25 35 55 ns switching characteristics over the operating range (continued) [14] parameter description 7c024/024a/0241?15 7c025/0251?15 7c024/024a/0241?25 7c025/0251?25 7c024/024a/0241?35 7c025/0251?35 7c024/024a/0241?55 7c025/0251?55 unit min max min max min max min max timing parameter test conditions [22] max unit icc dr1 at vcc dr = 2v 1.5 ma data retention mode 4.5v 4.5v v cc ? ? 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih notes 20. test conditions used are load 2. 21. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 22. ce = v cc , v in = gnd to v cc , t a = 25 ? c. this parameter is guaranteed but not tested. [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 11 of 19 switching waveforms notes 23. r/w i s high for read cycles 24. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 25. oe = v il . 26. address valid prior to or coincident with ce transition low. 27. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha figure 4. read cycle no. 1 (either port address access) [23, 24, 25] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current figure 5. read cycle no. 2 (either port ce /oe access) [23, 26, 27] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce figure 6. read cycle no. 3 (either port) [23, 25, 26, 26, 27] [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 12 of 19 notes 28. r/w must be high during all address transitions. 29. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 30. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at t he end of write cycle. 31. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 32. to access ram, ce = v il , sem = v ih . 33. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 34. transition is measured 500 mv from steady state with a 5 pf load (including scope and jig). this parameter is sampled and n ot 100% tested. 35. during this period, the i/o pins are in the out put state, and input signals must not be applied. 36. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe figure 7. write cycle no. 1: r/w controlled timing [28, 29, 30, 31] [34] [34] [31] [32,33] note 35 note 35 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa figure 8. write cycle no. 2: ce controlled timing [28, 29, 30, 36] [32,33] [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 13 of 19 notes 37. ce = high for the duration of the above timing (both write and read cycle). 38. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 39. semaphores are reset (available to both ports) at cycle start. 40. if t sps is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable . switching waveforms (continued) t sop t aa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ?a 2 figure 9. semaphore read after write timing, either side [37] match t sps a 0l ?a 2l match r/w l sem l a 0r ?a 2r r/w r sem r figure 10. timing diagram of semaphore contention [38, 39, 40] [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 14 of 19 switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l figure 11. timing diagram of read with busy (m/s =high) [41] t pwe r/w busy t wb t wh figure 12. write timing with busy input (m/s =low) note 41. ce l = ce r = low [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 15 of 19 note 42. if t ps is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side busy is asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r figure 13. busy timing diagram no.1 (ce arbitration) [42] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: figure 14. busy timing diag ram no.2 (address arbitration) [42] left address valid first: [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 16 of 19 figure 15. interrupt timing diagrams notes 43. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 44. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) write fff (1fff cy7c025) t wc right side clears int r : t ha read fff t rc t inr write ffe (1ffe cy7c025) t wc right side sets int l : left side sets int r : left side clears int l : read ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (1fff cy7c025) (1ffe cy7c025) [43] [44] [44] [44] [43] [44] [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 17 of 19 ordering code definitions ordering information ( 4k x16 dual-port sram) speed (ns) ordering code package name package type operating range 15 cy7c024-15axc a100 100-pin pb free thin quad flat pack commercial 25 cy7c024-25axc a100 100-pin pb free thin quad flat pack commercial cy7c024a-25jxc a100 84-pin pb free plastic leaded chip carrier cy7c024-25axi a100 100-pin pb free thin quad flat pack industrial cy7c024-25jxi j83 84-pin pb free plastic leaded chip carrier 55 CY7C024-55AXC a100 100-pin pb free thin quad flat pack commercial cy7c024-55jxc j83 84-pin pb free plastic leaded chip carrier ordering information (8k x 16 dual-port sram) speed (ns) ordering code package name package type operating range 25 cy7c025-25axc a100 100-pin pb free thin quad flat pack commercial cy7c025-25axi a100 100-pin pb free thin quad flat pack industrial cy7c025-25jxi j83 84-pin pb free plastic leaded chip carrier 55 cy7c025-55axc a100 100-pin pb free thin quad flat pack commercial ordering information (4k x 18 dual-port sram) speed (ns) ordering code package name package type operating range 15 cy7c0241-15axi a100 100-pin pb free thin quad flat pack industrial 25 cy7c0241-25axc a100 100-pin pb free thin quad flat pack commercial ordering information (8k x 18 dual-port sram) speed (ns) ordering code package name package type operating range 15 cy7c0251?15axc a100 100-pin pb free thin quad flat pack commercial temperature range: x = c or i c = commercial; i = industrial package type: xx = ax or jx ax = 100-pin tqfp (pb-free) jx = 84-pin plcc (pb-free) speed grade (15 ns / 25 ns / 55 ns) 02xx = 024 / 024a / 025 / 0241 / 0251 = part identifier cy7c = cypress srams cy7c 02xx - xx xx x [+] feedback
cy7c024/024a/0241 cy7c025/0251 document #: 38-06035 rev. *f page 18 of 19 package diagrams figure 16. 100-pin pb-free thin plastic quad flat pack (tqfp) a100 figure 17. 84-pin pb free plastic leaded chip carrier j83 51-85048 *d 51-85006 *b [+] feedback
document #: 38-06035 rev. *f revised october 13, 2010 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c024/024a/0241 cy7c025/0251 ? cypress semiconductor corporation, 2001-2010. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy7c024/024a/0241, cy7c 025/0251 4k x 16/18 and 8k x 16/18 dual-port static ram with sem, int, busy document number: 38-06035 rev. ecn no. orig. of change submission date description of change ** 110177 szv 09/29/01 change from spec number: 38-00255 to 38-06035 *a 122286 rbi 12/27/02 power up requirements added to maximum ratings information *b 236754 ydt see ecn removed cross in formation from features section *c 279132 ruy see ecn added lead (pb)-free packaging information *d 2623540 vkn/pyrs 12/17/08 added cy7c024a part updated ordering information table *e 2896038 rame 03/19/10 removed inactive parts from ordering information table updated package diagram *f 3058184 admu 10/13/2010 rem oved cy7c024-55ac from ordering information (4k x16 dual-port sram) and cy7c025-25ac from ordering information (8k x 16 dual-port sram) and added ordering code definitions . [+] feedback

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